A secondary clock network is often used within an integrated circuit, such as a programmable logic device (e.g., a complex programmable logic device (CPLD) or a field programmable gate array (FPGA)), to provide a routing resource for clock, control, and high fan-out data within the integrated circuit. A drawback of conventional secondary clock networks is the limited number of channels (e.g., four global channels), with a typical application often requiring to route more high fan-out signals than can be accommodated by the secondary clock network. Consequently, the additional high fan-out signals must be routed through general routing resources (e.g., a general interconnect of the PLD), which is costly in terms of routing resources utilized.
Another drawback of a conventional high fan-out network is that the network may use full or partial clock lines that require local routing resources. For example, the logic blocks of the PLD may be implemented with the local routing resources (e.g., multiplexers and drivers or buffers) to support the high fan-out signal routing of the network. However, typical PLD software for logic placement is generally not limited to a single row or column and therefore a significant amount of local routing resources within the PLD may need to be used to provide the vertical and horizontal routing. Furthermore, depending upon the clock line length and due to long line loading and distance, the buffers and other routing resources may be large, slow, cause timing skew, and may require a tri-stable bus structure to support the long clock line length.
As a result, there is a need for improved techniques for high fan-out signal routings, such as for example for a secondary clock network within a PLD.